1. Field of the Invention
The present invention relates to a novel bipolar junction transistor (BJT) device and a method of fabricating the same, and more particularly, relates to a method which can create lithographically defined, vertically all-through n-type region on an originally p-type silicon substrate. Such a vertically all-through n-type region can replace the expitaxy layer and buried layer applied in fabricating BJT devices.
2. Description of the Related Art
MOS transistors are general devices applied in the design and fabrication of integrated circuits, because of their low power dissipation and high integration density. However, the voltage rating, operating frequency (speed), and current driving capacity of MOS transistors cannot compare with those of BJT devices. Therefore, in some applications of integrated circuits requiring a high voltage rating, high operating speed, and large current driving capacity, most integrated circuits, such as power transistor ICs, RF ICs and power switch ICs, etc. are made of BJT devices.
Though conventional BJT ICs have high voltage ratings, the area of the isolation region is quite large. Furthermore, during the process of fabricating conventional BJT devices, buried layers and epitaxy layers must be formed, and the dopant of the buried layer may diffuse out, so that the epitaxy layer incurs auto-doping of the dopant during the growth process. Further, the cost for growing an epitaxy layer in conventional BJT devices is high, and the throughput is low.
Referring to FIG. 1A to FIG. 1E , a process for fabricating a conventional NPN IC BJT device is shown in cross section view. First, a mask layer 2 is formed on a semiconductor p-type substrate 1. The mask layer 2, for example, can be an oxide layer with a thickness of between 50.about.100 .ANG.. The mask layer 2 is patterned by a photolithography process, and then is etched to form an opening 3, locally revealing the p-type substrate 1, as shown in FIG. 1A. The implantation by using arsenic ions with a flux density of about 10.sup.15 atoms/cm.sup.2 and with an energy of about 30 K eV is carried out, thereby forming an n.sup.+ diffusion region serving as a buried layer 4 in the p-type substrate 1 at opening 3. After implantation, the mask layer 2 is removed, as depicted in FIG. 1B. An n-type lightly doping epitaxy layer 5 with a doping concentration of about 10.sup.15 .about.10.sup.16 atoms/cm.sup.3 is formed over the buried layer 4 and the p-type substrate 1. If the BJT device is for low voltage applications then the thickness of the epitaxy layer 5 is about 1.about.10 .mu.m, and if the BJT device is for high voltage applications then the thickness of the epitaxy layer 5 is about 10.about.500 .mu.m. An oxide layer 6 is further formed over the epitaxy layer 5. The oxide layer 6 is patterned by a photolithography process and then is etched to form openings 7, as depicted in FIG. 1C. Then, boron ions are driven into the epitaxy layer 5 through the openings 7 such that p-type diffusion regions 8 are formed, serving as isolation regions, wherein the diffusion regions 8 extends into the p-type substrate 1, as depicted in FIG. 1D. Finally, a p-type base region 9, n-type collector regions 10, and an n.sup.+ -type doped polysilicon layer 11 are formed respectively, thereby completing the process for fabricating the conventional NPN IC BJT, as depicted in FIG. 1E.
Clearly, the conventional NPN BJT fabricated by the method (prior art) described above has the following drawbacks.
First, a junction capacitor C.sub.sub (not shown) exists between the buried layer 4 and the p-type substrate 1, and thus the operating speed of the BJT will be limited.
Second, out-diffusion and auto-doping problems are induced, and thus the epitaxy layer will be corrupted, during the growth period of the epitaxy layer, as described above.
Third, in the prior art, the n-type epitaxy layer is isolated from the p-type diffusion regions and the p-type silicon substrate. In general, the p-type diffusion regions for isolation formed in the epitaxy layer always pass through the epitaxy layer to the p-type substrate. The thickness of the epitaxy layer is thick for high voltage rating applications. Therefore, the diffusion region for isolation is also great. Consequently, the lateral diffusion width of the diffusion region also becomes large, such that the control of device dimension becomes more complicated and the device integrity of integrated circuit is reduced. The trench isolation commonly used in the prior art, is only appropriate for BJT devices operating at low voltages. For trench isolation, a trench of deep depth must be formed first, and then oxide or a polysilicon layer is grown to fill the trench. Such trench isolation is very difficult to implement and costly, especially for deep trenches. Further, lattice defects in the epitaxy layer and substrate will be induced.
Fourth, for the applications of high power and/or high voltage rating BJT devices, thicker epitaxy layers are required. However, the process for growing an epitaxy layer is costly and the throughput of epitaxy layer is low, so growing an epitaxy layer is not economical to fabricate BJT devices for high power and high voltage rating applications.
Fifth, in the prior art, another way of isolation is to use local oxidation of silicon, LOCOS, but this cannot provide complete isolation for IC BJT devices of great longitudinal depth (thick epitaxy layer).
Sixth, the structural topology of BJT devices is vertical and thus an epitaxy layer is required. The topology of the MOS transistor is horizontal, and not requiring epitaxy layer. Therefore, the way for incorporating the processes of fabricating a BJT device with that of fabricating a MOS transistor is very difficult.